The demand for improvements of the performance of a transistor is increasing with the acceleration of the integration of a semiconductor device, and the size of a memory cell is decreasing with an increase in the integration degree of a semiconductor device.
However, a parasitic capacitance occurs due to a pre-metal dielectric that fills a gap between a transistor and a gate spacer formed in fabricating the transistor.
A parasitic capacitance is one of the main factors reducing the operation speed of a high-integration device, and the occurrence of a parasitic capacitance greatly affects the characteristics of the device.
Recently, research is being conducted to apply low-dielectric materials to an interlayer dielectric process in order to reduce a delay time caused by such a parasitic capacitance.